Performance Evaluation of Fpga-based Cellular Automata Accelerators

The scientific community has been using FPGA-based computation engines as cellular automata (CA) accelerators for some time now. With the recent advent of more advanced FPGA logic it becomes necessary to better understand the mapping of CA to these systems. In this paper, we present a methodology to predict the performance of running such CA on specific FPGA hardware before engineering the design in reality. This will help to determine the optimal values for the various parameters that control the application and the given FPGA hardware specifications. The model is validated for two different types of two-dimensional CA algorithms.